The controller supports a quarter-rate burst-length-of-two configuration, and can issue up to eight read and/or write commands per controller clock cycle. The controller may have to reduce the actual number of commands issued to avoid banking and bus turnaround violations. If you use QDR-IV devices with banked operation, you cannot access the same bank in the same memory clock cycle. Write latency is much shorter than read latency, therefore you must be careful not to place write data at the same time that read data is driven on the bus, on the same port. In addition, when switching between read and write operations, a delay may be required to avoid signal reflection and allow enough time for dynamic on-chip termination (OCT) to work. If necessary, the scheduler in the controller can delay the issuing of commands to avoid these issues.
For information on the AFI, refer to AFI 4.0 Specification in Functional Description - Arria 10 EMIF IP.
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