External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

16.13.1. Addressing

Each reconfigurable feature of the interface has an associated memory address; however, this address is placement dependent. If Altera PHYLite for Parallel Interfaces IP cores and the Arria 10 External Memory Interfaces IP cores share the same I/O column, you must track the addresses of the interface lanes and the pins. Addressing is done at the 32-bit word boundary, where avl_address[1:0] are always 00.

Address Map

These points apply to the following table:

  • id[3:0] refers to the Interface ID parameter.
  • lane_addr[7:0] refers to the address of a given lane in an interface. The Fitter sets this address value. You can query this in the Parameter Table Lookup Operation Sequence as described in Address Lookup section of the Intel PHYLite for Parallel Interfaces IP Core User Guide.
  • pin[4:0] refers to the physical location of the pin in a lane. You can use the Fitter to automatically determine a pin location or you can manually set the pin location through .qsf assignment. Refer to the Parameter Table Lookup Operation Sequence as described in Address Lookup section of the Intel PHYLite for Parallel Interfaces IP Core User Guide for more information.
Feature Avalon Address R/W Address CSR R Control Value
Field Range
Pin Output Phase {id[3:0],3'h4,lane_addr[7:0],pin{4:0],8'D0} {id[3:0],3'h4,lane_addr[7:0],pin{4:0],8'E8} Phase Value 12..0

Minimum Setting: Refer to

Maximum Setting: Refer to

Incremental Delay: 1/128th VCO clock period

Note: The pin output phase switches from the CSR value to the Avalon value after the first Avalon write. It is only reset to the CSR value on a reset of the interface.
Reserved 1 31..13
Pin PVT Compensated Input Delay {id[3:0],3'h4,lane_addr[7:0],4'hC,lgc_sel[1:0],pin_off[2:0],4'h0}
  • lgc_sel[1:0] is:
    • 2'b01 for DQ [5:0]
    • 2'b10 for DQ [11:6]
  • pin_off[2:0] :
    • 3'h0: DQ [0], DQ [6]
    • 3’h1: DQ [1], DQ [7]
    • 3’h2: DQ [2], DQ [8]
    • 3’h3: DQ [3], DQ [9]
    • 3’h4: DQ [4], DQ [10]
    • 3’h5: DQ [5], DQ [11]
Not supported Delay Value 8..0

Minimum Setting: 0

Maximum Setting: 511 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Reserved 1 11..9
Enable 12

0 = Delay value is 0.

1 = Select delay value from Avalon register

Reserved 1 31..13
Strobe PVT compensated input delay 2 {id[3:0],3'h4,lane_addr[7:0],4'hC,lgc_sel[1:0],3'h6,4'h0}
  • lgc_sel[1:0] = 2'b01
Not supported Delay Value 9..0

Minimum Setting: 0

Maximum Setting: 1023 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Reserved 1 11..10
Enable 12

0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP core instantiation.

1 = Select delay value from Avalon register

Reserved 1 31..13
Strobe enable phase 2 {id[3:0],3'h4,lane_addr[7:0],4'hC,lgc_sel[1:0],3'h7,4'h0}
  • lgc_sel[1:0] = 2'b01

{id[3:0],3'h4,lane_addr[7:0],4'hC,9'h198}

Phase Value 12..0

Minimum Setting: Refer to

Maximum Setting: Refer to

Incremental Delay: 1/128th VCO clock period

Reserved 1 14..13
Enable 15

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Reserved 1 31..16
Strobe enable delay 2 {id[3:0],3'h4,lane_addr[7:0],4'hC,9'h008} {id[3:0],3'h4,lane_addr[7:0],4'hC,9'h1A8} Delay Value 5..0

Minimum Setting: 0 external clock cycles

Maximum Setting: 63 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Reserved 1 14..6
Enable 15

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Reserved 1 31..16
Read valid delay 2 {id[3:0],3'h4,lane_addr[7:0],4'hC,9'h00C} {id[3:0],3'h4,lane_addr[7:0],4'hC,9'h1A4} Delay Value 6..0

Minimum Setting: 0 external clock cycles

Maximum Setting: 127 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Reserved 1 14..7
Enable 15

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Reserved 1 31..16
Internal VREF Code {id[3:0],3'h4,lane_addr[7:0],4'hC,9'h014} Not supported VREF Code 5..0 Refer to Calibrated VREF Settings in the Intel PHYLite for Parallel Interfaces IP Core User Guide.
     
Reserved 1 31..6 9
  1. Reserved bit ranges must be zero.
  2. Modifying these values must be done on all lanes in a group.
Note: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

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