External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.1. Supported Memory Protocols

The following table lists the external memory protocols supported by Arria® 10 devices.
Table 40.  Supported Memory Protocols
Protocol Hard Controller and Hard PHY Soft Controller and Hard PHY PHY Only
DDR4 Yes Yes
DDR3 Yes Yes
LPDDR3 Yes Yes
RLDRAM 3 Third party Yes
QDR II/II+/II+ Xtreme Yes
QDR-IV Yes

Memory protocols not listed above are not supported by the Arria® 10 EMIF IP; however, you can implement a custom memory interface for these protocols using the Altera PHYLite Megafunction.

LPDDR3 is supported for simulation, compilation, and timing. Hardware support for LPDDR3 will be provided in a future release.

Note: To achieve maximum top-line spec performance for a DDR4 interface, both read data bus inversion and periodic OCT calibration must be enabled. For maximum top-line spec performance for a QDR-IV interface, read data bus inversion must be enabled.

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