External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.5.3. PLL Reference Clock Sharing

In Stratix® 10, every I/O bank contains a PLL, meaning that it is not necessary to share PLLs in the interest of conserving resources. Nonetheless, it is often desirable to share PLLs for other reasons.

You might want to share PLLs between interfaces for the following reasons:

  • To conserve pins.
  • When combined with the use of the balanced PLL reference clock tree, to allow the clock signals at different interfaces to be synchronous and aligned to each other. For this reason, interfaces that share core clock signals must also share the PLL reference clock signal.

To implement PLL reference clock sharing, in your RTL code connect the PLL reference clock signal at your design's top-level to the PLL reference clock port of multiple interfaces.

To share a PLL reference clock, the following requirements must be met:

  • Interfaces must expect a reference clock signal of the same frequency.
  • Interfaces must be placed in the same column.
  • Interfaces must be placed at adjacent bank locations.