2.16.1. Stratix® 10 Ping Pong PHY Feature Description
With the Ping Pong PHY, address and command signals from two independent controllers are multiplexed onto shared buses by delaying one of the controller outputs by one full-rate clock cycle. The result is 1T timing, with a new command being issued on each full-rate clock cycle. The following figure shows address and command timing for the Ping Pong PHY.
The command signals CS, ODT, and CKE have two signals (one for ping and one for pong); the other address and command signals are shared.
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