External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents Implementing a x8 Interface with Hard Memory Controller

The following diagram illustrates the use of a single I/O bank to implement a DDR3 or DDR4 x8 interface using the hard memory controller.
Figure 84. Single Bank x8 Interface With Hard Controller

In the above diagram, shaded cells indicate resources that are in use.

Note: For information on the I/O lanes and pins in use, consult the pin table for your device or the <variation_name>/altera_emif_arch_nf_140/<synth|sim>/<variation_name>_altera_emif_arch_nf_140_<unique ID>_readme.txt file generated with your IP.