External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents Implementing a x72 Interface with Hard Memory Controller

The following diagram illustrates one possible implementation of a DDR3 or DDR4 x72 interface using the hard memory controller.

Note that only the hard memory controller in the address and command bank is used. Similarly, only the clock phase alignment block of the address and command bank is used to generate clock signals for the FPGA core.

Figure 85. Multi-Bank x72 Interface With Hard Controller

In the above diagram, shaded cells indicate resources that are in use.

Note: For information on the I/O lanes and pins in use, consult the pin table for your device or the <variation_name>/altera_emif_arch_nf_140/<synth|sim>/<variation_name>_altera_emif_arch_nf_140_<unique ID>_readme.txt file generated with your IP.