External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

3.4.1. Arria® 10 EMIF Architecture: I/O Subsystem

The I/O subsystem consists of two columns inside the core of Arria® 10 devices.

Each column can be thought of as loosely analogous to an I/O bank.

Figure 81.  Arria® 10 I/O Subsystem

The I/O subsystem provides the following features:

  • General-purpose I/O registers and I/O buffers
  • On-chip termination control (OCT)
  • I/O PLLs for external memory interfaces and user logic
  • Low-voltage differential signaling (LVDS)
  • External memory interface components, as follows:
    • Hard memory controller
    • Hard PHY
    • Hard Nios processor and calibration logic
    • DLL