External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.4.9. Arria® 10 EMIF Architecture: Clock Phase Alignment

In Arria® 10 external memory interfaces, a global clock network clocks registers inside the FPGA core, and the PHY clock network clocks registers inside the FPGA periphery. Clock phase alignment circuitry employs negative feedback to dynamically adjust the phase of the core clock signal to match the phase of the PHY clock signal.

The clock phase alignment feature effectively eliminates the clock skew effect in all transfers between the core and the periphery, facilitating timing closure. All Arria® 10 external memory interfaces employ clock phase alignment circuitry.

Figure 91. Clock Phase Alignment Illustration


Figure 92. Effect of Clock Phase Alignment


Did you find the information on this page useful?

Characters remaining:

Feedback Message