External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

3.5.4. Core Clock Network Sharing

It is often desirable or necessary for multiple memory interfaces to be accessible using a single clock domain in the FPGA core.

You might want to share core clock networks for the following reasons:

  • To minimize the area and latency penalty associated with clock domain crossing.
  • To minimize consumption of core clock networks.

Multiple memory interfaces can share the same core clock signals under the following conditions:

  • The memory interfaces have the same protocol, rate, frequency, and PLL reference clock source.
  • The interfaces reside in the same I/O column.
  • The interfaces reside in adjacent bank locations.

For multiple memory interfaces to share core clocks, you must specify one of the interfaces as master and the remaining interfaces as slaves. Use the Core clocks sharing setting in the parameter editor to specify the master and slaves.

In your RTL, connect the clks_sharing_master_out signal from the master interface to the clks_sharing_slave_in signal of all the slave interfaces. Both the master and slave interfaces expose their own output clock ports in the RTL (e.g. emif_usr_clk, afi_clk), but the signals are equivalent, so it does not matter whether a clock port from a master or a slave is used.

Core clock sharing necessitates PLL reference clock sharing; therefore, only the master interface exposes an input port for the PLL reference clock. All slave interfaces use the same PLL reference clock signal.