External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.15.3. Configuring Your EMIF IP for Use with the Debug Toolkit

The Arria® 10 EMIF Debug Interface IP core contains the access point through which the EMIF Debug Toolkit reads calibration data collected by the Nios II sequencer.

Connecting an EMIF IP Core to an Arria® 10 EMIF Debug Interface

For the EMIF Debug Toolkit to access the calibration data for an Arria® 10 EMIF IP core, you must connect one of the EMIF cores in each I/O column to an Arria® 10 EMIF Debug Interface IP core. Subsequent EMIF IP cores in the same column must connect in a daisy chain to the first.

There are two ways that you can add the Arria 10 EMIF Debug Interface IP core to your design:

  • When you generate your EMIF IP core, on the Diagnostics tab, select Add EMIF Debug Interface for the EMIF Debug Toolkit/On-Chip Debug Port; you do not have to separately instantiate an Arria® 10 EMIF Debug Interface core. This method does not export an Avalon-MM slave port. You can use this method if you require only EMIF Debug Toolkit access to this I/O column; that is, if you do not require On-Chip Debug Port access, or PHYLite reconfiguration access.
  • When you generate your EMIF IP core, on the Diagnostics tab, select Export for the EMIF Debug Toolkit/On-Chip Debug Port. Then, separately instantiate an Arria® 10 EMIF Debug Interface core and connect its to_ioaux interface to the cal_debug interface on the EMIF IP core. This method is appropriate if you want to also have On-Chip Debug Port access to this I/O column, or PHYLite reconfiguration access.

For each of the above methods, you must assign a unique interface ID for each external memory interface in the I/O column, to identify that interface in the Debug Toolkit. You can assign an interface ID using the dropdown list that appears when you enable the Debug Toolkit/On-Chip Debug Port option.

Daisy-Chaining Additional EMIF IP Cores for Debugging

After you have connected an Arria® 10 EMIF Debug Interface to one of the EMIF IP cores in an I/O column, you must then connect subsequent EMIF IP cores in that column in a daisy-chain manner. If you don't require debug capabilities for a particular EMIF IP core, you do not have to connect that core to the daisy chain.

To create a daisy chain of EMIF IP cores, follow these steps:

  1. On the first EMIF IP core, select Enable Daisy-Chaining for EMIF Debug Toolkit/On-Chip Debug Port to create an Avalon-MM interface called cal_debug_out.
  2. On the second EMIF IP core, select Export as the EMIF Debug Toolkit/On-Chip Debug Port mode, to export an Avalon-MM interface called cal_debug.
  3. Connect the cal_debug_out interface of the first EMIF core to the cal_debug interface of the second EMIF core.
  4. To connect more EMIF cores to the daisy chain, select the Enable Daisy-Chaining for EMIF Debug Toolkit/On-Chip Debug Port option on the second core, connect it to the next core using the Export option as described above. Repeat the process for subsequent EMIF cores.

If you place any PHYLite cores with dynamic reconfiguration enabled into the same I/O column as an EMIF IP core, you should instantiate and connect the PHYLite cores in a similar way. See the Altera PHYLite for Memory Megafunction User Guide for more information.

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