ID 683841
Date 7/24/2019
Public

## 3.18.1. Bus Width and AFI Ratio

In cases where the AFI clock frequency is one-half or one-quarter of the memory clock frequency, the AFI data must be twice or four times as wide, respectively, as the corresponding memory data. The ratio between AFI clock and memory clock frequencies is referred to as the AFI ratio. (A half-rate AFI interface has an AFI ratio of 2, while a quarter-rate interface has an AFI ratio of 4.)

In general, the width of the AFI signal depends on the following three factors:

• The size of the equivalent signal on the memory interface. For example, if a[15:0] is a DDR3 address input and the AFI clock runs at the same speed as the memory interface, the equivalent afi_addr bus will be 16-bits wide.
• The data rate of the equivalent signal on the memory interface. For example, if d[7:0] is a double-data-rate QDR II input data bus and the AFI clock runs at the same speed as the memory interface, the equivalent afi_write_data bus will be 16-bits wide.
• The AFI ratio. For example, if cs_n is a single-bit DDR3 chip select input and the AFI clock runs at half the speed of the memory interface, the equivalent afi_cs_n bus will be 2-bits wide.

The following formula summarizes the three factors described above:

AFI_width = memory_width * signal_rate * AFI_RATE_RATIO
Note: The above formula is a general rule, but not all signals obey it. For definite signal-size information, refer to the specific table.