External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.13. Back-to-Back User-Controlled Refresh for Hard Memory Controller

The following waveform illustrates the recommended Arria® 10 model for back-to-back user-controlled refreshes, for optimized hard memory controller performance.
Figure 103. 

You should deassert the refresh request after the refresh acknowledgement pulse is received. You can implement a timer to keep track of the tRFC status before asserting a refresh request. Failure to deassert the Refresh request can delay access to the rank not in refresh.

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