External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents

3.10. Back-to-Back User-Controlled Refresh Usage in Arria® 10

The following diagram illustrates the back-to-back refresh model for optimized hard memory controller (HMC) performance in Arria® 10 devices.

For optimal performance, ensure that you deassert the Refresh request after receiving the acknowledgement pulse. You can implement a timer to track tRFC before asserting the next Refresh request. Failure to deassert the Refresh request can delay memory access to the rank not in refresh.

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