External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
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2.17.4.2. AFI Write Sequence Timing Diagrams

The following timing diagrams illustrate the relationships between the write command and corresponding write data and write enable signals, in full, half, and quarter rate.

Write sequences with wlat=0

For half rate and quarter rate, when the write command is sent on the first memory clock in a PHY clock (for example, afi_cs_n[0] = 0), that access is called aligned access; otherwise it is called unaligned access. You may use either aligned or unaligned access, or you may use both, but you must ensure that the distance between the write command and the corresponding write data are constant on the AFI interface. For example, if a command is sent on the second memory clock in a PHY clock, the write data must also start at the second memory clock in a PHY clock.

Figure 66. AFI Write Data Full-Rate, wlat=0

The following diagrams illustrate both aligned and unaligned access. The first three write commands are aligned accesses where they were issued on LSB of afi_command. The fourth write command is unaligned access where it was issued on a different command slot. AFI signals must be shifted accordingly, based on the command slot.

Figure 67. AFI Write Data Half-Rate, wlat=0

Figure 68. AFI Write Data Quarter-Rate, wlat=0

Write sequences with wlat=non-zero

The afi_wlat is a signal from the PHY. The controller must delay afi_dqs_burst, afi_wdata_valid, afi_wdata and afi_dm signals by a number of PHY clock cycles equal to afi_wlat, which is a static value determined by calibration before the PHY asserts cal_success to the controller. The following figures illustrate the cases when wlat=1. Note that wlat is in the number of PHY clocks and therefore wlat=1 equals 1, 2, and 4 memory clocks delay, respectively, on full, half and quarter rate.

Figure 69. AFI Write Data Full-Rate, wlat=1

Figure 70. AFI Write Data Half-Rate, wlat=1

Figure 71. AFI Write Data Quarter-Rate, wlat=1

DQS burst

The afi_dqs_burst signal must be asserted one or two complete memory clock cycles earlier to generate DQS preamble. DQS preamble is equal to one-half and one-quarter AFI clock cycles in half and quarter rate, respectively.

A DQS preamble of two is required in DDR4, when the write preamble is set to two clock cycles.

The following diagrams illustrate how afi_dqs_burst must be asserted in full, half, and quarter-rate configurations.

Figure 72. AFI DQS Burst Full-Rate, wlat=1

Figure 73. AFI DQS Burst Half-Rate, wlat=1

Figure 74. AFI DQS Burst Quarter-Rate, wlat=1

Write data sequence with DBI (DDR4 and QDRIV only)

The DDR4 write DBI feature is supported in the PHY, and when it is enabled, the PHY sends and receives the DBI signal without any controller involvement. The sequence is identical to non-DBI scenarios on the AFI interface.

Write data sequence with CRC (DDR4 only)

When the CRC feature of the PHY is enabled and used, the controller ensures at least one memory clock cycle between write commands, during which the PHY inserts the CRC data. Sending back to back write command would cause functional failure. The following figures show the legal sequences in CRC mode.

Entries marked as 0 and RESERVE must be observed by the controller; no information is allowed on those entries.

Figure 75. AFI Write Data with CRC Half-Rate, wlat=2

Figure 76. AFI Write Data with CRC Quarter-Rate, wlat=2

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