External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.13.3.2. AFI Address and Command Signals

The address and command signals for AFI 3.0 encode read/write/configuration commands to send to the memory device. The address and command signals are single-data rate signals.
Table 10.  Address and Command Signals 

Signal Name

Direction

Width

Description

afi_ba

Input

AFI_BANKADDR_WIDTH

Bank address. (Not applicable for LPDDR3.)

afi_cke

Input

AFI_CLK_EN_WIDTH

Clock enable.

afi_cs_n

Input

AFI_CS_WIDTH

Chip select signal. (The number of chip selects may not match the number of ranks; for example, RDIMMs and LRDIMMs require a minimum of 2 chip select signals for both single-rank and dual-rank configurations. Consult your memory device data sheet for information about chip select signal width.) (Matches the number of ranks for LPDDR3.)

afi_ras_n

Input

AFI_CONTROL_WIDTH

RAS# (for DDR2 and DDR3 memory devices.)

afi_we_n

Input

AFI_CONTROL_WIDTH

WE# (for DDR2, DDR3, and RLDRAM II memory devices.)

afi_cas_n

Input

AFI_CONTROL_WIDTH

CAS# (for DDR2 and DDR3 memory devices.)

       

afi_ref_n

Input

AFI_CONTROL_WIDTH

REF# (for RLDRAM II memory devices.)

afi_rst_n

Input

AFI_CONTROL_WIDTH

RESET# (for DDR3 and DDR4 memory devices.)

afi_odt

Input

AFI_CLK_EN_WIDTH

On-die termination signal for DDR2, DDR3, and LPDDR3 memory devices. (Do not confuse this memory device signal with the FPGA’s internal on-chip termination signal.)

afi_mem_clk_disable

Input

AFI_CLK_PAIR_COUNT

When this signal is asserted, mem_clk and mem_clk_n are disabled. This signal is used in low-power mode.

afi_wps_n

Output

AFI_CS_WIDTH

WPS (for QDR II/II+ memory devices.)

afi_rps_n

Output

AFI_CS_WIDTH

RPS (for QDR II/II+ memory devices.)

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