Each LE has the following features:

• A four-input look-up table (LUT) that can implement any function of four variables
• A programmable register
• A carry chain connection
• A register chain connection
• The ability to drive the following interconnects:
  • Local
  • Row
  • Column
  • Register chain
  • Direct link
• Register packing support
• Register feedback support

• Normal mode
• Arithmetic mode

These operating modes use LE resources differently. Both LE modes have six available inputs and LAB-wide signals.

The Intel^® Quartus^® Prime software automatically chooses the appropriate mode for common functions, such as counters, adders, subtractors, and arithmetic functions, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions.

You can also create special-purpose functions that specify which LE operating mode to use for optimal performance.

In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT. The Intel^® Quartus^® Prime Compiler automatically selects the carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal mode support packed registers and register feedback.

The LE in arithmetic mode implements a two-bit full adder and basic carry chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode.

Each LAB consists of the following:

• 16 logic elements (LEs)—smallest logic unit in Intel^® Cyclone^® 10 LP devices
• LE carry chains—carry chains propagated serially through each LE within an LAB
• LAB control signals—dedicated logic for driving control signals to LEs within an LAB
• Local interconnect—transfers signals between LEs in the same LAB
• Register chains—transfers the output of one LE register to the adjacent LE register in an LAB

The Intel^® Quartus^® Prime Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local and register chain connections for performance and area efficiency.

The direct link connection minimizes the use of row and column interconnects to provide higher performance and flexibility. The direct link connection enables the neighboring elements from left and right to drive the local interconnect of an LAB. The elements are:

• LABs
• PLLs
• M9K embedded memory blocks
• Embedded multipliers

Each LE can drive up to 48 LEs through local and direct link interconnects.

The control signals include:

• Two clock signals
• Two clock enable signals
• Two asynchronous clear signals
• One synchronous clear signal
• One synchronous load signal

You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously.

Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals.

An LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. Intel^® Cyclone^® 10 LP devices only support either a preset or asynchronous clear signal.

In addition to the clear port, Intel^® Cyclone^® 10 LP devices provide a chip-wide reset pin (DEV_CLRn) to reset all registers in the device. An option set before compilation in the Intel^® Quartus^® Prime software controls this pin. This chip-wide reset overrides all other control signals.

Intel^® Cyclone^® 10 LP embedded memory supports the following general features:

• 8,192 memory bits per block (9,216 bits per block including parity).
• Independent read-enable (rden) and write-enable (wren) signals for each port.
• Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
• Variable port configurations.
• Single-port and simple dual-port modes support for all port widths.
• True dual-port (one read and one write, two reads, or two writes) operation.
• Byte enables for data input masking during writes.
• Two clock-enable control signals for each port (port A and port B).
• Initialization file to preload memory content in RAM and ROM modes.

The clock-enable control signal controls the clock entering the input and output registers and the entire M9K memory block. This signal disables the clock so that the M9K memory block does not see any clock edges and does not perform any operations.

The rden and wren control signals control the read and write operations for each port of the M9K memory blocks. You can disable the rden or wren signals independently to save power whenever the operation is not required.

You can perform parity checking for error detection with the parity bit along with internal logic resources. The M9K memory blocks support a parity bit for each storage byte. You can use this bit as either a parity bit or as an additional data bit. No parity function is actually performed on this bit. If error detection is not desired, you can use the parity bit as an additional data bit.

The byte enable features mask the input data to enable the writing of only specific bytes. The unwritten bytes retain the previous values. The write enable signal, wren, together with the byte enable signal, byteena, control the write operations on the RAM blocks. By default, the byteena signal is enabled (high) and only the wren signal controls the writing.

The M9K blocks support byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits. In True Dual-Port memory configuration, byte enables are available only if both PortA and PortB data widths of each M9K memory blocks are multiples of 8 or 9 bits.

Byte enables operate in a one-hot fashion. The LSB of the byteena signal corresponds to the LSB of the data bus. For example, if byteena = 01 and you are using a RAM block in ×18 mode, data[8:0] is enabled and data[17:9] is disabled. Similarly, if byteena = 11, both data[8:0] and data[17:9] are enabled.

Byte enables are active high. The byte enable registers do not have a clear port.

The read-during-write operation occurs when a read operation and a write operation target the same memory location at the same time.

The read-during-write operation operates in the following ways:

• Same-port
• Mixed-port

You can implement two single-port memory blocks in a single block under the following conditions:

• Each of the two independent block sizes is less than or equal to half of the M9K block size. The maximum data width for each independent block is 18 bits wide.
• Each of the single-port memory blocks is configured in single-clock mode.

By default, the address clock enable signal, addressstall, is disabled and the signal is active low. While the addressstall signal is high (addressstall = 1), the address register holds the previous address value.

Support of asynchronous clear in the M9k memory block:

• Read address registers—input registers other than read address registers are not supported. Asserting asynchronous clear to the read address register during a read operation might corrupt the memory content.
• Output registers—if applied to output registers, the asynchronous clear signal clears the output registers and the effects are immediate. If your RAM does not use output registers, you can still clear the RAM outputs using the output latch asynchronous clear feature.
• Output latches

The M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple operation modes. The M9K memory blocks do not support asynchronous (unregistered) memory inputs.

The RAM: 1-Port IP core implements the single-port RAM memory mode.

The RAM: 2-PORT IP core implements the simple dual-port RAM and true dual-port RAM memory modes.

The ROM: 1-PORT IP core implements the single-port ROM memory mode.

This IP core implements the dual-port ROM memory mode. The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.

The Shift Register (RAM-based) IP core contains additional features not found in a conventional shift register. You can use the memory blocks as a shift-register block to save logic cells and routing resources. You can cascade memory blocks to implement larger shift registers.

The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.

• Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to implement single- and dual-clock FIFO buffers in your design.
• Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain.
• The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.

In all clock modes, asynchronous clear is available only for output latches and output registers. For independent clock mode, this is applicable on port A and port B.

If you perform a simultaneous read/write to the same address location using the read or write clock mode, the output read data is unknown. If you want the output read data to be a known value, use single-clock or input/output clock mode and then select the appropriate read-during-write behavior in the RAM: 1-PORT and RAM: 2-PORT IP cores.

The following equation defines the port width configuration: Memory depth (number of words) × Width of the data input bus.

• If your port width configuration (either the depth or the width) is more than the amount an internal memory block can support, additional memory blocks (of the same type) are used. For example, if you configure your M9K as 512 × 36, which exceeds the supported port width, two 512 × 18 M9Ks are used to implement your RAM.
• In addition to the supported configuration provided, you can set the memory depth to a non-power of two, but the actual memory depth allocated can vary. The variation depends on the type of resource implemented.
• If the memory is implemented in dedicated memory blocks, setting a non-power of two for the memory depth reflects the actual memory depth.
• When you implement your memory using dedicated memory blocks, refer to the Fitter report to check the actual memory depth.

The Set the maximum block depth parameter allows you to set the maximum block depth of the dedicated memory block you use. You can slice the memory block to your desired maximum block depth. For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).

Use this parameter to save power usage in your devices and to reduce the total number of memory blocks used. However, this parameter might increase the number of LEs and affects the design performance.

When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices.

The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.

This table lists the valid range of maximum block depth for M9K memory blocks.

The IP parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Intel recommends that you set the value of the Set the maximum block depth parameter to Auto if you are unsure of the appropriate maximum block depth to set or the setting is not important for your design. The Auto setting enables the Compiler to select the maximum block depth with the appropriate port width configuration for the type of internal memory block of your memory.

There are several considerations that require your attention to ensure the success of your designs.

The Intel^® Cyclone^® 10 LP devices, either alone or as DSP device coprocessors, improves the price-to-performance ratios of DSP systems. The Intel^® Cyclone^® 10 LP devices are optimized for applications that benefit from an abundance of parallel processing resources, which include video and image processing, intermediate frequency (IF) modems used in wireless communications systems, and multi-channel communications and video systems.

For multiplications greater than 18 x 18, the Intel^® Quartus^® Prime software cascades the multiplier blocks to form wider or deeper logic structures. There are no restrictions on the data width of the multiplier but the greater the data width, the slower the multiplication process.

You can control the operation of the embedded multiplier blocks using the following options:

• Parameterize the relevant IP cores with the Quartus Prime parameter editor
• Infer the multipliers directly with VHDL or Verilog HDL

Additionally, you can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The LUTs contain partial results from the multiplication of input data with coefficients that implements variable depth and width high-performance soft multipliers. Using soft multipliers increases the number of available multipliers in the device.

Each multiplier input signal can be sent through a register independently of other input signals. For example, you can send the multiplier Data A signal through a register and send the Data B signal directly to the multiplier.

All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals.

All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals.

You can also use embedded multipliers of the Intel^® Cyclone^® 10 LP devices to implement multiplier adder and multiplier accumulator functions. The multiplier portion of the function is implemented using embedded multipliers. The adder or accumulator function is implemented in logic elements (LEs).

You can configure each embedded multiplier to support a single 18 x 18 multiplier for input widths of 10 to 18 bits.

The following figure shows the embedded multiplier configured to support an 18-bit multiplier.

You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits.

The following figure shows the embedded multiplier configured to support two 9-bit multipliers.

This chapter describes the hierarchical clock networks and phase-locked loops (PLLs) with advanced features in the Intel^® Cyclone^® 10 LP devices. It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time, allowing you to sweep PLL output frequencies and dynamically adjust the output clock phase shift.

The Intel^® Quartus^® Prime software enables the PLLs and their features without external devices.

The Intel^® Cyclone^® 10 LP device provides up to 16 dedicated clock pins (CLK[15..0]) that can drive up to 20 global clocks (GCLKs). Intel^® Cyclone^® 10 LP devices support three dedicated clock pins on the left side and four dedicated clock pins on the top, right, and bottom sides of the device except 10CL006 and 10CL010 devices. 10CL006 and 10CL010 devices only support three dedicated clock pins on the left side and four dedicated clock pins on the right side of the device.

GCLKs drive throughout the entire device, feeding all device quadrants. All resources in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks, and M9K memory blocks) can use GCLKs as clock sources. Use these clock network resources for control signals, such as clock enables and clears fed by an external pin. Internal logic can also drive GCLKs for internally generated GCLKs and asynchronous clears, clock enables, or other control signals with high fan-out.

The clock control block drives the GCLKs. Clock control blocks are located on each side of the device, close to the dedicated clock input pins. GCLKs are optimized for minimum clock skew and delay.

In Intel^® Cyclone^® 10 LP devices, dedicated clock input pins, PLL counter outputs, dual-purpose clock I/O inputs, and internal logic can all feed the clock control block for each GCLK. The output from the clock control block in turn feeds the corresponding GCLK. The GCLK can drive the PLL input if the clock control block inputs are outputs of another PLL or dedicated clock input pins.

The maximum number of clock control blocks per Intel^® Cyclone^® 10 LP device is 20.

The control block has two functions:

• Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK, and internal logic input)
• GCLK network power down (dynamic enable and disable)

The inputs to the five clock control blocks on each side of the Intel^® Cyclone^® 10 LP device must be chosen from among the following clock sources:

• Three or four clock input pins, depending on the specific device
• Five PLL counter outputs
• Two DPCLK pins and two CDPCLK pins from both the left and right sides and four DPCLK pins from both the top and bottom
• Five signals from internal logic

From the clock sources listed above, only two clock input pins, two PLL clock outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into any given clock control block.

Out of these six inputs to any clock control block, the two clock input pins and two PLL outputs are dynamically selected to feed a GCLK. The clock control block supports static selection of the signal from internal logic.

You can disable an Intel^® Cyclone^® 10 LP device’s GCLK (power down) using both static and dynamic approaches. In the static approach, configuration bits are set in the configuration file generated by the Intel^® Quartus^® Prime software, which automatically disables unused GCLKs. The dynamic clock enable or disable feature allows internal logic to control clock enable or disable the GCLKs in Intel^® Cyclone^® 10 LP devices.

When a clock network is disabled, all the logic fed by the clock network is in an off-state, thereby reducing the overall power consumption of the device. This function is independent of the PLL and is applied directly on the clock network.

You can set the input clock sources and the clkena signals for the GCLK multiplexers through the Intel^® Quartus^® Prime software using the ALTCLKCTRL IP core.

Intel^® Cyclone^® 10 LP devices support clkena signals at the GCLK network level. This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the output clock, the PLL does not need a resynchronization or re-lock period because the circuit gates off the clock at the clock network level. In addition, the PLL can remain locked independent of the clkena signals because the loop-related counters are not affected.

The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization.

Intel recommends using the clkena signals when switching the clock source to the PLLs or the GCLK. The recommended sequence is:

1. Disable the primary output clock by de-asserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the clkena signal. The exact number of clock cycles you must wait before enabling the secondary clock is design-dependent. You can build custom logic to ensure glitch-free transition when switching between different clock sources.

Intel^® Cyclone^® 10 LP devices only have the general purpose PLLs. The general purpose PLLs are used for general-purpose applications in the FPGA fabric and periphery such as external memory interfaces.

Intel^® Cyclone^® 10 LP devices have up to four general purpose PLLs that provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The general I/O pins cannot drive the PLL clock input pins.

Each PLL of Intel^® Cyclone^® 10 LP devices supports one single-ended clock output or one differential clock output. Only the C0 output counter can feed the dedicated external clock outputs without going through the GCLK. Other output counters can feed other I/O pins through the GCLK.

Each pin of a differential output pair is 180° out of phase. The Intel^® Quartus^® Prime software places the NOT gate in your design into the I/O element to implement 180° phase with respect to the other pin in the pair. The clock output pin pairs support the same I/O standards as standard output pins.

Intel^® Cyclone^® 10 LP PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as GPIO pins if external PLL clocking is not required.

Intel^® Cyclone^® 10 LP PLLs support up to five different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.

Input and output delays are fully compensated by the PLL only if you are using the dedicated clock input pins associated with a given PLL as the clock sources.

When driving the PLL using the GCLK network, the input and output delays may not be fully compensated in the Intel^® Quartus^® Prime software.

If the data and clock arrive at the same time at the input pins, the phase relationship between the data and clock remains the same at the data and clock ports of any I/O element input register.

You can use this mode for source synchronous data transfers. Data and clock signals at the I/O element experience similar buffer delays as long as both signals use the same I/O standard.

Source synchronous mode compensates for clock network delay, including any difference in delay between the following two paths:

• Data pin to I/O element register input
• Clock input pin to the PLL phase frequency detector (PFD) input

For all data pins clocked by a source synchronous mode PLL, set the input pin to the register delay chain in the I/O element to zero in the Intel^® Quartus^® Prime software. All data pins must use the PLL COMPENSATED logic option in the Intel^® Quartus^® Prime software.

In no compensation mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because clock feedback into the PFD does not pass through as much circuitry. Both the PLL internal and external clock outputs are phase-shifted with respect to the PLL clock input.

An internal clock in normal mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Intel^® Quartus^® Prime software timing analyzer reports any phase difference between the two. In normal mode, the PLL fully compensates the delay introduced by the GCLK network.

In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. When using this mode, use the same I/O standard for the input clock and output clocks to ensure clock alignment at the input and output pins.

Each Intel^® Cyclone^® 10 LP PLL provides clock synthesis for PLL output ports using M/(N × post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match f_IN (M/N). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO value is the least common multiple of the output frequencies that meets its frequency specifications. For example, if output frequencies required from one PLL are 33 and 66 MHz, the Intel^® Quartus^® Prime software sets the VCO to 660 MHz (the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale counters scale down the VCO frequency for each output port.

There is one pre-scale counter, N, and one multiply counter, M, per PLL, with a range of 1 to 512 for both M and N. The N counter does not use duty cycle control because the purpose of this counter is only to calculate frequency division. There are five generic post-scale counters per PLL that can feed GCLKs or external clock outputs. These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The post-scale counters range from 1 to 256 with any non-50% duty cycle setting. The sum of the high/low count values chosen for a design selects the divide value for a given counter.

The Intel^® Quartus^® Prime software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTPLL IP core.

Phase alignment between output counters is determined using the t_{PLL_PSERR} specification.

The Intel^® Cyclone^® 10 LP PLLs support post-scale counter cascading to create counters larger than 512. This is implemented by feeding the output of one C counter into the input of the next C counter.

When cascading counters to implement a larger division of the high-frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings.

For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.

Post-scale counter cascading is automatically set by the Intel^® Quartus^® Prime software in the configuration file. Post-scale counter cascading cannot be performed using PLL reconfiguration.

The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters. You can achieve the duty cycle setting by a low and high time count setting for the post-scale counters. The Intel^® Quartus^® Prime software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. The post-scale counter value determines the precision of the duty cycle. The precision is defined by 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty cycle choices between 5 to 90%.

Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.

You can use the pfdena, areset, and locked signals to observe and control the PLL operation and resynchronization.

The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application, such as a system that turns on the redundant clock if the previous clock stops running. Your design can automatically perform clock switchover when the clock is no longer toggling, or based on the user control signal, clkswitch.

The Intel^® Cyclone^® 10 LP PLLs support a fully configurable clock switchover capability.

When the current reference clock is not present, the clock-sense block automatically switches to the backup clock for PLL reference. The clock switchover circuit also sends out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to implement a custom switchover circuit. You can select a clock source at the backup clock by connecting it to the inclk1 port of the PLL in your design.

There are two ways to use the clock switchover feature:

• Use the switchover circuitry for switching from inclk0 to inclk1 running at the same frequency. For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal that controls the multiplexer select input. In this case, inclk1 becomes the reference clock for the PLL. This automatic switchover can switch back and forth between the inclk0 and inclk1 clocks any number of times, when one of the two clocks fails and the other clock is available.
• Use the clkswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. Choose the secondary clock frequency so the VCO operates in the recommended frequency range. Also, set the M, N, and C counters accordingly to keep the VCO operating frequency in the recommended range.

If you are using the automatic switchover, you must switch input clocks with the manual override feature with the clkswitch input.

The following figure shows an example of a waveform illustrating the switchover feature when controlled by clkswitch. In this case, both clock sources are functional and inclk0 is selected as the reference clock. A low-to-high transition of the clkswitch signal starts the switchover sequence. The clkswitch signal must be high for at least three clock cycles (at least three of the longer clock period if inclk0 and inclk1 have different frequencies). On the falling edge of inclk0, the reference clock of the counter, muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference, and the activeclock signal changes to indicate which clock is currently feeding the PLL.

In this mode, the activeclock signal mirrors the clkswitch signal. As both blocks are still functional during the manual switch, neither clkbad signals go high. Because the switchover circuit is positive edge-sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the process repeats. The clkswitch signal and the automatic switch only works depending on the availability of the clock that is switched to. If the clock is unavailable, the state machine waits until the clock is available.

When CLKSWITCH = 1, it overrides the automatic switchover function. As long as clkswitch signal is high, further switchover action is blocked.

The Intel^® Cyclone^® 10 LP PLLs support manual switchover, in which the clkswitch signal controls whether inclk0 or inclk1 is the input clock to the PLL. The characteristics of a manual switchover are similar to the manual override feature in an automatic clock switchover, in which the switchover circuit is edge-sensitive. When the clkswitch signal goes high, the switchover sequence starts. The falling edge of the clkswitch signal does not cause the circuit to switch back to the previous input clock.

Use the following guidelines to design with clock switchover in PLLs:

• Clock loss detection and automatic clock switchover require the inclk0 and inclk1 frequencies be within 20% of each other. Failing to meet this requirement causes the clkbad0 and clkbad1 signals to function improperly. When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 20%. However, differences between the two clock sources (frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL ensures that the correct phase relationships are maintained between the input and output clocks.
• Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start the manual clock switchover event. Failing to meet this requirement causes the clock switchover to malfunction.
• Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the switchover happens, the low-bandwidth PLL propagates the stopping of the clock to the output slower than the high-bandwidth PLL. The low-bandwidth PLL filters out jitter on the reference clock. However, the low-bandwidth PLL also increases lock time.
• After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to re-lock is dependent on the PLL configuration.
• If the phase relationship between the input clock to the PLL and output clock from the PLL is important in your design, assert areset for 10 ns after performing a clock switchover. Wait for the locked signal (or gated lock) to go high before re-enabling the output clocks from the PLL.
• Disable the system during switchover if the system is not tolerant to frequency variations during the PLL resynchronization period. You can use the clkbad0 and clkbad1 status signals to turn off the PFD (pfdena = 0) so the VCO maintains its last frequency. You can also use the switchover state machine to switch over to then secondary clock. Upon enabling the PFD, output clock enable signals (clkena) can disable clock outputs during the switchover and resynchronization period. After the lock indication is stable, the system can re-enable the output clock or clocks.
• The VCO frequency gradually decreases when the primary clock is lost and then increases as the VCO locks on to the secondary clock, as shown in the following figure. After the VCO locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency.

The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter. The Intel^® Cyclone^® 10 LP PLLs provide advanced control of the PLL bandwidth using the programmable characteristics of the PLL loop, including loop filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for open loop PLL response.

Phase shift is used to implement a robust solution for clock delays in Intel^® Cyclone^® 10 LP devices. Phase shift is implemented with a combination of the VCO phase output and the counter starting time. The VCO phase output and counter starting time are the most accurate methods of inserting delays, because they are based only on counter settings that are independent of process, voltage, and temperature.

You can phase shift the output clocks from the Intel^® Cyclone^® 10 LP PLLs in one of two ways:

• Fine resolution using VCO phase taps
• Coarse resolution using counter starting time

Fine resolution phase shifts are implemented by allowing any of the output counters (C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference clock. This allows you to adjust the delay time with a fine resolution.

The following equation shows the minimum delay time that you can insert using this method.

For example, if f_REF is 100 MHz, N = 1, and M = 8, then f_VCO = 800 MHz, and Φ_fine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that depends on reference clock frequency and counter settings.

Coarse resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks.

You can use the coarse and fine phase shifts to implement clock delays in Intel^® Cyclone^® 10 LP devices.

Intel^® Cyclone^® 10 LP devices support dynamic phase shifting of VCO phase taps only. The phase shift is configurable for any number of times. Each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly.

Two PLLs are cascaded to each other through the clock network. If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting.

PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In Intel^® Cyclone^® 10 LP PLLs, you can reconfigure both counter settings and phase shift the PLL output clock in real time. You can also change the charge pump and loop filter components, which dynamically affects PLL bandwidth. You can use these PLL components to update the output clock frequency, PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.

The ability to reconfigure the PLL in real time is useful in applications that might operate at multiple frequencies. It is also useful in prototyping environments, allowing you to sweep PLL output frequencies and adjust the output clock phase dynamically. For instance, a system generating test patterns is required to generate and send patterns at 75 or 150 MHz, depending on the requirements of the device under test. Reconfiguring PLL components in real time allows you to switch between two such output frequencies in a few microseconds.

You can also use this feature to adjust clock-to-out (t_CO) delays in real time by changing the PLL output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL settings.

The following PLL components are configurable in real time:

• Pre-scale counter (N)
• Feedback counter (M)
• Post-scale output counters (C0-C4)
• Charge pump current (I_CP)
• Loop filter components (R, C)

You can dynamically adjust the charge pump current (I_CP) and loop filter components (R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth.

The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, not all counters update simultaneously.

You can configure the multiply or divide values and duty cycle of the post-scale counters in real time. Each counter has an 8-bit high time setting and an 8-bit low time setting. The duty cycle is the ratio of output high or low time to the total cycle time, which is the sum of the two.

The post-scale counters have two control bits:

• rbypass—For bypassing the counter
• rselodd—For selecting the output clock duty cycle

When the rbypass bit is set to 1, it bypasses the counter, resulting in a division by one. When this bit is set to 0, the PLL computes the effective division of the VCO output frequency based on the high and low time counters. The PLL implements this duty cycle by transitioning the output clock from high-to-low on the rising edge of the VCO output clock.

For example, if the post-scale divide factor is 10, the high and low count values are set to 5 and 5 respectively, to achieve a 50–50% duty cycle. However, a 4 and 6 setting for the high and low count values, respectively, would produce an output clock with 40–60% duty cycle.

The rselodd bit indicates an odd divide factor for the VCO output frequency with a 50% duty cycle. The PLL implements this duty cycle by transitioning the output clock from high-to-low on a falling edge of the VCO output clock.

For example, if the post-scale divide factor is 3, the high and low time count values are 2 and 1 respectively, to achieve this division. This implies a 67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor. When you set rselodd = 1, subtract 0.5 cycles from the high time and add 0.5 cycles to the low time.

The calculation for the example is shown as follows:

• High time count = 2 cycles
• Low time count = 1 cycle
• rselodd = 1 effectively equals:
  • High time count = 1.5 cycles
  • Low time count = 1.5 cycles
  • Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count

Intel^® Cyclone^® 10 LP devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the PLL. The Intel^® Cyclone^® 10 LP PLLs can track a spread-spectrum input clock as long as it is in the input jitter tolerance specifications and the modulation frequency of the input clock is below the PLL bandwidth, that is specified in the fitter report. Intel^® Cyclone^® 10 LP devices cannot generate spread-spectrum signals internally.

Intel^® Cyclone^® 10 LP devices offer highly configurable GPIOs with these features:

• Support for various single-ended and differential I/O standards.
• Programmable current strength, bus hold, pull-up resistors, and delays.
• Programmable slew rate control to optimize signal integrity.
• Optional open-drain output for each I/O pin.
• True and emulated LVDS buffers with LVDS SERDES implemented using logic elements in the device core.
• Programmable pre-emphasis for the true LVDS output buffers.
• Calibrated on-chip series termination (R_S OCT) or driver impedance matching (R_S) for single-endd I/O standards.
• Support for hot socketing implementation.

• ALTIOBUF—supports operations of the GPIO components.
• ALTLVDS—supports operations of the high-speed source-synchronous SERDES.
• ALTDDIO—supports configuration and implementation of double data rate I/O registers.

The Intel^® Cyclone^® 10 LP I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer.

Each IOE contains one input register, two output registers, and two output-enable (OE) registers:

• The two output registers and two OE registers are used for DDR applications.
• You can use the input registers for fast setup times and output registers for fast clock-to-output times.
• You can use the OE registers for fast clock-to-output enable times.

You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various single-ended and differential I/O standards.

The only exception is HSTL-12 Class II, which is only supported in column I/O banks.

There are two types of I/O banks in Intel^® Cyclone^® 10 LP devices:

• Row I/O banks—I/O banks 1, 2, 5, and 6, located on the left and right side of the device
• Column I/O banks—I/O banks 3, 4, 7, and 8, located on the top and bottom side of the device

Only the column I/O banks support the 1.2 V HSTL Class II I/O standard. Both row and column I/O banks support all the other single-ended and differential I/O standards that the Intel^® Cyclone^® 10 LP device supports.

Use an external resistor to pull the signal to a logic high.

The bus-hold circuitry holds the signal on an I/O pin at its last-driven state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the V_CCIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.

The bus-hold circuitry is not available on dedicated clock pins.

For the specific sustaining current for each V_CCIO voltage level driven through the resistor and for the overdrive current used to identify the next driven input level, refer to the device datasheet.

The Intel^® Cyclone^® 10 LP device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated configuration pins, dedicated clock pins, or JTAG pins.

If you enable the weak pull-up resistor, you cannot use the bus-hold feature.

• Fast slew rate—provides high-speed transitions for high-performance systems.
• Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew rate control. The slew rate control affects both the rising and falling edges.

Each pin can have a different delay value to ensure signals within a bus have the same delay going into or out of the device.

Each dual-purpose clock input pin provides a programmable delay to the global clock networks.

There are two paths in the IOE for an input to reach the logic array. Each of the two paths can have a different delay. This allows you to adjust delays from the pin to the internal logic element (LE) registers that reside in two different areas of the device. You must set the two combinational input delays with the input delay from pin to internal cells logic option in the Intel^® Quartus^® Prime software for each path. If the pin uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Intel^® Quartus^® Prime software.

The IOE registers in each I/O block share the same source for the preset or clear features. You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete. If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.

The PCI clamp diode is available and enabled by default in the Intel^® Quartus^® Prime software for the following I/O standards:

• 3.3 V LVTTL/3.3 V LVCMOS
• 3.0 V LVTTL/3.0 V LVCMOS
• 2.5 V LVTTL/2.5 V LVCMOS
• 3.0 V PCI/PCI-X

Pre-emphasis increases the amplitude of the high-frequency component of the output signal. This increase compensates for the frequency-dependent attenuation along the transmission line.

The overshoot introduced by the extra current occurs only during change of state switching. This overshoot increases the output slew rate but does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.

According to JEDEC standards, the following I/O standards do not specify a recommended termination scheme:

• 3.3-V LVTTL
• 3.0 V LVTTL/3.0 V LVCMOS
• 2.5 V LVTTL/2.5 V LVCMOS
• 1.8 V LVTTL/1.8 V LVCMOS
• 1.5 V LVCMOS
• 1.2 V LVCMOS
• 3.0 V PCI/PCI-X

The devices support driver impedance matching to match the impedance of the transmission line, which is typically 25 Ω or 50 Ω. Impedance matching uses the capabilities of the output driver and is subject to a certain degree of variation, depending on the process, voltage, and temperature.

The Intel^® Cyclone^® 10 LP devices support serial (R_S) OCT for single-ended output pins and bidirectional pins.

• For bidirectional pins, OCT is active for output only.
• V_CCIO and V_REF must be compatible for all I/O pins to enable R_S OCT in an I/O bank.
• I/O standards that support different R_S values can reside in the same I/O bank if their V_CCIO and V_REF do not conflict.
• Dedicated configuration pins and JTAG pins do not support impedance matching or series termination.

In Intel^® Cyclone^® 10 LP devices, there is one OCT calibration block on each side of the device. The calibration block supports both I/O banks on the side on which it is located:

• If you enable OCT calibration for both I/O banks on the same device side, use the same V_CCIO on both banks.
• If the V_CCIO values of the I/O banks on the same side are not the same, you can use OCT calibration only on the I/O bank that contains the calibration block.

Each OCT calibration block comes with a pair of RUP and RDN pins. During calibration, the RUP and RDN pins are each connected through an external 25 Ω ±1% or 50 Ω ±1% resistor for respective on-chip series termination value of 25 Ω or 50 Ω:

• RUP—connected to VCCIO.
• RDN—connected to GND.

The OCT calibration circuit compares the external resistors to the internal resistance using comparators. The OCT calibration block uses the comparators' output to dynamically adjust buffer impedance.

During calibration, the resistance of the RUP and RDN pins varies. To estimate of the maximum possible current through the external calibration resistors, assume a minimum resistance of 0 Ω on the RUP and RDN pins.

The RUP and RDN pins go to a tri-state condition when calibration is completed or not running. These two pins are dual-purpose I/Os and function as regular I/Os if you do not use the calibration circuit.

• For LVDS transmitters and receivers, Intel^® Cyclone^® 10 LP devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
• For the LVDS serializer/deserializer (SERDES), Intel^® Cyclone^® 10 LP devices use logic elements (LE) registers.
• The device uses shift registers, internal phase-locked loops (PLLs), and I/O cells to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data.

The Intel^® Cyclone^® 10 LP left and right I/O banks (row I/Os) support true LVDS transmitters. The top and bottom I/O banks support emulated LVDS transmitters with external resistors.

For the LVDS receiver, you require an external 100 Ω termination resistor between the two signals at the input buffer.

The Intel^® Cyclone^® 10 LP top, bottom, and right side I/O banks support the Bus LVDS I/O standard. For the Bus LVDS transmitter, Intel^® Cyclone^® 10 LP devices use emulated differential output. For the Bus LVDS receiver, Intel^® Cyclone^® 10 LP devices use the true LVDS input buffer. The transmitter and receiver share the same pins. Intel^® Cyclone^® 10 LP devices require an output enable (OE) signal to tristate the output buffers when the LVDS input buffer receives a signal.

To support RSDS, mini-LVDS, and PPDS output standards, Intel^® Cyclone^® 10 LP devices conform to the following specifications:

• National Semiconductor Corporation RSDS Interface Specification
• Texas Instruments mini-LVDS Interface Specification
• National Semiconductor Corporation PPDS Interface Specification

Intel^® Cyclone^® 10 LP I/O banks support RSDS, mini-LVDS, and PPDS output standards:

• The right I/O banks support true RSDS, mini-LVDS, and PPDS transmitters.
• The top and bottom I/O banks support emulated RSDS, mini-LVDS, and PPDS transmitters with external resistors.

A resistor network is required to attenuate the output voltage swing to meet RSDS, mini-LVDS, and PPDS specifications when using emulated transmitters. You can modify the resistor network values to reduce power or improve the noise margin.

For an RSDS interface, you can use a single external resistor instead of three. The single-resistor solution reduces the external resistor count while still achieving the required RSDS signaling level. However, the performance is lower than with a three-resistor network.

Intel^® Cyclone^® 10 LP devices support the LVPECL input standard at the dedicated clock input pins only. The LVPECL receiver requires an external 100 Ω termination resistor between the two signals at the input buffer.

LVPECL requires AC coupling when the common mode voltage of the output buffer is higher than the LVPECL input common mode voltage on the Intel^® Cyclone^® 10 LP device.

In the following figures, the 50 Ω resistors at the receiver are external to the device.

DC-coupled LVPECL is supported if the LVPECL output common mode voltage is in the LVPECL input buffer specification of the Intel^® Cyclone^® 10 LP devices.

Intel^® Cyclone^® 10 LP devices support Differential SSTL-2 and Differential SSTL-18 I/O standards. The Differential SSTL output standard is only supported at the PLL#_CLKOUT pins using two single-ended SSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output programmed to have opposite polarity.

The Differential SSTL input standard is supported on the GCLK pins only, treating differential inputs as two single-ended SSTL and only decoding one of them.

The Differential SSTL I/O standard requires two differential inputs with an external reference voltage (V_REF) and an external termination voltage (V_TT) of 0.5 × V_CCIO to which termination resistors are connected.

Intel^® Cyclone^® 10 LP devices support Differential 1.8 V HSTL, Differential 1.5 V HSTL, and Differential 1.2 V HSTL I/O standards.

The differential HSTL input standard is available on GCLK pins only, treating the differential inputs as two single-ended HSTL and only decoding one of them.

The differential HSTL output standard is only supported at the PLL#_CLKOUT pins using two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output programmed to have opposite polarity.

The Differential HSTL I/O standard requires two differential inputs with an external reference voltage (V_REF), as well as an external termination voltage (V_TT) of 0.5 × V_CCIO to which termination resistors are connected.

Intel^® Cyclone^® 10 LP devices implement the SERDES in LEs. You must set proper timing constraints to indicate whether the SERDES captures the data as expected or otherwise. You can set the timing constraints using the Timing Analyzer tool in the Intel^® Quartus^® Prime software or manually in the Synopsys* Design Constraints (.sdc) file.

Conventions used for the equation:

• RSKM—the timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise.
• Time unit interval (TUI)—time period of the serial data.
• SW—the period of time that the input data must be stable to ensure that the LVDS receiver samples the data successfully. The SW is a device property and varies according to device speed grade.
• TCCS—the timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the t_CO variation, clock, and clock skew.

You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS receiver can sample the data:

• A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly.
• A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly.

The Intel^® Quartus^® Prime software checks your pin connections with respect to the I/O assignment and placement rules to ensure proper device operation.

These rules depend on device density, package, I/O assignments, voltage assignments and other factors that are not fully described in this chapter.

This setting allows the Intel^® Quartus^® Prime software to automatically check for illegal pad placements according to the DC guidelines.

The programmable current strength setting affects the amount of DC current that an output pin can source or sink. Determine if the current strength setting is sufficient for the external resistive load condition on the output pin.

• If you use a V_REF group for voltage-referenced I/O standards, connect the VREF pin for that group to the appropriate voltage level.
• If you do not use all the V_REF groups in the I/O bank for voltage-referenced I/O standards, you can use the VREF pin in the unused voltage-referenced groups as regular I/O pins.
• The VREF pins are shorted together within the same I/O bank. If you use multiple V_REF groups in the same I/O bank, you must power all the VREF pins with the same voltage level.

For example, if you have SSTL-2 Class I input pins in I/O bank 1 and you place them all in the VREFB1N[0] group, you must power VREFB1N[0] with 1.25 V. You can use the remaining VREFB1N[1..3] pins, if available, as I/O pins.

Each Intel^® Cyclone^® 10 LP I/O bank has its own V_CCIO pins and supports only one V_CCIO of 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V. An I/O bank can simultaneously support several I/O standards if the I/O standards use the same V_CCIO levels for input and output pins.

An I/O bank can simultaneously support several voltage-referenced standards if all the I/O standards use the same V_REF and V_CCIO values. For example, For examples:

• SSTL-2 and SSTL-18 I/O standards require different V_REF values. If you implement both of these I/O standards in the device, you must assign them to I/O pins in different I/O banks.
• If you implement SSTL-2 and 2.5 V LVCMOS I/O standards, both with V_CCIO of 2.5 V and V_REF of 1.25 V, you can assign them to I/O pins in the same I/O bank.

If you are designing LVTTL/LVCMOS inputs with Intel^® Cyclone^® 10 LP devices, follow these guidelines:

• All pins accept input voltage (V_I) up to a maximum limit (3.6 V) stated in the recommended operating conditions in the device datasheet.
• Whenever the input level is higher than the bank's V_CCIO, expect higher leakage current.
• The LVTTL or LVCMOS I/O standard input pins can only conform to the V_IH and V_IL levels according to the bank's voltage level.

If you use an Intel^® Cyclone^® 10 LP device as a receiver in a 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS systems, you must manage the overshoot or undershoot to stay within the absolute maximum ratings and the recommended operating conditions. Refer to the device datasheet.

The Intel^® Quartus^® Prime software can validate your pin placement and check for illegal pad placements. Refer to the related information.

Use the following general guidelines to improve signal quality:

• Base board designs on controlled differential impedance. Calculate and compare all parameters, such as trace width, trace thickness, and the distance between two differential traces.
• Maintain equal distance between traces in differential I/O standard pairs as much as possible. Routing the pair of traces close to each other maximizes the common-mode rejection ratio (CMRR).
• Longer traces have more inductance and capacitance. These traces must be as short as possible to limit signal integrity issues.
• Place termination resistors as close to receiver input pins as possible.
• Use surface mount components.
• Avoid 90° corners on board traces.
• Use high-performance connectors.
• Design backplane and card traces so that trace impedance matches the impedance of the connector and termination.
• Keep an equal number of vias for both signal traces.
• Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the TCCS value increases.
• Limit vias because they cause discontinuities.
• Keep switching transistor-to-transistor logic (TTL) signals away from differential signals to avoid possible noise coupling.
• Do not route TTL clock signals to areas under or above the differential signals.
• Analyze system-level signals.