Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

2.7.2. Supported PIPE Features

PIPE Gen1 and Gen2 configurations support different features.
Table 117.  Supported Features for PIPE Configurations
Protocol Feature


(2.5 Gbps)


(5 Gbps)

x1, x2, x4 link configurations Yes Yes
PCIe-compliant synchronization state machine Yes Yes
Total 600 ppm clock rate compensation between transmitter reference clock and receiver reference clock Yes Yes
Transmitter driver electrical idle Yes Yes
Receiver detection Yes Yes
8B/10B encoding/decoding disparity control Yes Yes
Power state management Yes Yes
Receiver PIPE status encoding pipe_rxstatus[2:0] Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate No Yes
Dynamic transmitter margining for differential output voltage control No Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB No Yes
PCS PMA interface width (bits) 10 10
Receiver Electrical Idle Inference (EII) Your implementation in the FPGA fabric Your implementation in the FPGA fabric

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