Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.2. Input Reference Clock Sources

The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

Cyclone® 10 GX transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:

  • Dedicated reference clock pins
  • Reference clock network
  • The output of another fPLL with PLL cascading
  • Receiver input pins
  • Global clock or core clock 33

For the best jitter performance, Intel recommends placing the reference clock as close as possible to the transmit PLL. For protocol jitter compliance at a data rate > 10 Gbps, place the reference clock pin in the same triplet as the transmit PLL. The following protocols require the reference clock to be placed in same bank as the transmit PLL:

  • OC-192 and 10 GPON
Note: For optimum performance, the reference clock of transmit PLL is recommended to be from a dedicated reference clock pin in the same bank.
Figure 122. Input Reference Clock Sources
Note: To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
33 Not available for CMU.