Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Interlaken Mode

In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To implement the deskew process, implement an FSM that controls the FIFO operation based on available FPGA input and output flags.

For example, after frame lock is achieved, data is written after the first alignment word (SYNC word) is found on that channel. As a result, rx_enh_fifo_pempty (FIFO partially empty flag ) of that channel goes low. You must monitor the rx_enh_fifo_pempty and rx_enh_fifo_pfull flags of all channels. If rx_enh_fifo_pempty flags from all channels deassert before any rx_enh_fifo_pfull flag asserts, which implies alignment word has been found on all lanes of the link, you start reading from all the FIFOs by asserting rx_enh_fifo_rd_en. Otherwise, if a rx_enh_fifo_pfull flag from any channel goes high before a rx_enh_fifo_pempty flag deassertion on all channels, you must reset the FIFO by toggling the rx_enh_fifo_align_clr signal and repeating the process.

Figure 190. RX FIFO as Interlaken Deskew FIFO