Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

4.2. Transceiver PHY Implementation

Figure 146. Typical Transceiver PHY Implementation

Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver Reset Endpoints (TREs)34 .

Transceiver Reset Sequencer—The Quartus Prime software detects the presence of TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)34. The tx_analogreset and rx_analogreset requests from the reset controller (User coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the reset request to the TRS for scheduling. TRS schedules all the requested PMA resets and sends them back to TREs. You can use either Transceiver PHY Reset Controller or your own reset controller. However, for the TRS to work correctly, the required timing duration must be followed. See Figure 147 for required timing duration.

Note: The TRS IP is an inferred block and is not visible in the RTL. You have no control over this block.
CLKUSR connection—The clock to the TRS must be stable and free-running (100-125 MHz). By default, the Quartus Prime software automatically connects the TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for your own logic (feeding it to the core), you must instantiate altera_a10_xcvr_clock_module
altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));

For more information about the CLKUSR pin, refer to the Cyclone® 10 GX Pin Connection Guidelines.

Note: To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
34 There is only one centralized TRS instantiated for one or more Native PHY.