Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Implementing Single Channel x1 Non-Bonded Configuration

In x1 non-bonded configuration, the PLL source is local to the transceiver bank and the x1 clock network is used to distribute the clock from the PLL to the transmitter channel.

For a single channel design, a PLL is used to provide the clock to a transceiver channel.

Figure 138. PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded Configuration Example

To implement this configuration, instantiate a PLL IP core and a PHY IP core and connect them together as shown in the above figure.

Steps to implement a Single Channel x1 Non-Bonded Configuration

  1. Instantiate the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to use in your design.
  2. Configure the PLL IP core using the IP Parameter Editor.
    • For ATX PLL IP core, do not include the Master CGB.
    • For fPLL IP core, set the PLL feedback operation mode to direct.
    • For CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
  3. Configure the Native PHY IP core using the IP Parameter Editor .
    • Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .
  4. Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk output port of the PLL to IP to the corresponding tx_serial_clk0 input port of the Native PHY IP core. This port represents the input to the local CGB of the channel. The tx_serial_clk for the PLL represents the high speed serial clock generated by the PLL.

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