Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents x6/xN Bonding

In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.

The steps below explain the x6/xN bonding process:

  1. The ATX PLL or the fPLL generates a high speed serial clock.
  2. The PLL drives the high speed serial clock to the master CGB via the x1 clock network.
  3. The master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network.
  4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels within the same transceiver bank. The local CGB in each transceiver channel is bypassed.
  5. To drive the channels in adjacent transceiver banks, the x6 clock network drives the xN clock network. The xN clock network feeds the TX clock mutiplexer for the transceiver channels in these adjacent transceiver banks.