- 184.108.40.206. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 220.127.116.11. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 18.104.22.168. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
7.2.5. Capability Registers
Reading capability registers does not require bus arbitration. You can read them during the calibration process.
To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic Reconfiguration tab.
The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same hardware and change state (high/low) concurrently during calibration. The register bits 0x281[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. This feature cannot be enabled, when a Simplex TX and Simplex RX channel merging is involved. To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks.
Did you find the information on this page useful?