Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

2.7.11. How to Place Channels for PIPE Configurations

Instead of the fitter or software model, the hardware dictates all the placement restrictions. The restrictions are listed below:

  • The channels must be contiguous for bonded designs.
  • The master CGB is the only way to access x6 lines and must be used in bonded designs. The local CGB cannot be used to route clock signals to slave channels because the local CGB does not have access to x6 lines.

For ATX PLL placement restrictions, refer to the section "Transmit PLL Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.