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2.7.9. fPLL Ports for PIPE
Resets the PLL when asserted high. Needs to be connected to the Transceiver PHY Reset Controller pll_powerdown output.
Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.
High speed serial clock output port for GX channels. Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk[5:0] input of the native PHY IP.
For Gen1x2, x4 use the tx_bonding_clocks[5:0] output port to connect to the Native PHY IP.
For Gen2x2, x4 use the tx_bonding_clocks output port to connect to the Native PHY IP.
Active high status signal which indicates if PLL is locked.
This is the hclk required for PIPE interface.
For Gen1x1, x2, x4 use this port to drive the pipe_hclk_infor the PIPE interface.
For Gen2x1, x2, x4 use this port to drive the pipe_hclk_in for the PIPE interface.
Status signal which is asserted high when PLL calibration is in progress.
If this port is not enabled in Transceiver PHY Reset Controller, then perform logical OR with this signal and the tx_cal_busy output signal from Native PHY to input the tx_cal_busy on the reset controller IP.
Master CGB reset control.
Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. It is used for channel bonding, and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2, x4 connect the output from this port to the tx_bonding_clocks input on Native PHY.
For Gen2x1, this port is disabled.
For Gen2x2, x4 connect the output from this port to the tx_bonding_clocks input on Native PHY.
2-bit rate switch control input used for PCIe protocol implementation.
For Gen1, this port is N/A
For Gen 2x2, x4 connect the pipe_sw output from Native PHY to this port.
2-bit rate switch status output used for PCIe protocol implementation.
For Gen1, this port is N/A.
For Gen 2x2, x4 connect the pcie_sw_done[1:0] output from fPLL to the pipe_sw_done input of Native PHY .
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