Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Receiver Status

The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal pipe_rx_status[2:0] for each channel. This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rx_status[2:0] signal conforms to the PCIe specification.