Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Implementing Multi-Channel xN Non-Bonded Configuration

Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock sources used.

Figure 140. PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded ConfigurationIn this example, the same PLL is used to drive 10 channels across two transceiver banks.

Steps to implement a multi-channel xN non-bonded configuration

  1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded configuration.
    • Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for this example.
  2. Configure the PLL IP core using the IP Parameter Editor. Enable Include Master Clock Generation Block .
  3. Configure the Native PHY IP core using the IP Parameter Editor
    • Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
    • Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.
  4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
    • In this case, the PLL IP core has mcgb_serial_clk output port. This represents the xN clock line.
    • The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.
    • As shown in the figure above, connect the mcgb_serial_clk output port of the PLL IP core to the 10 tx_serial_clk input ports of the Native PHY IP core.
Figure 141. Multi-Channel x1/xN Non-Bonded ExampleThe ATX PLL IP core has a tx_serial_clk output port. This port can optionally be used to clock the six channels within the same transceiver bank as the PLL. These channels are clocked by the x1 network. The remaining four channels outside the transceiver bank are clocked by the xN clock network.