Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
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2.3. Cyclone® 10 GX Transceiver Protocols and PHY IP Support

Table 3.   Cyclone® 10 GX Transceiver Protocols and PHY IP Support
Protocol Transceiver PHY IP Core PCS Support Transceiver Configuration Rule Protocol Preset
PCIe Gen2 x1, x2, x4 Native PHY IP (PIPE) core/Hard IP for PCI Express 1 Standard Gen2 PIPE PCIe PIPE Gen2 x1 2
PCIe Gen1 x1, x2, x4 Native PHY IP (PIPE) core/Hard IP for PCI Express 1 Standard Gen1 PIPE User created 3
1000BASE-X Gigabit Ethernet Native PHY IP core Standard GbE GIGE - 1.25 Gbps
1000BASE-X Gigabit Ethernet with 1588 Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps 1588
10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low Latency
10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R 4
40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced PCS 5
Interlaken (CEI-6G-SR and CEI-11G-SR) 6 Native PHY IP core Enhanced Interlaken

Interlaken 10x12.5Gbps

Interlaken 6x10.3Gbps

Interlaken 1x6.25Gbps

OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom (Standard PCS) User created
SONET/SDH STS-192/STM-64 (10G) via SFP+/SFF-8431/CEI-11G Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-192/STM-64 (10G) via OIF SFI-5.1s/SxI-5/SFI-4.2 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET STS-96 (5G) via OIF SFI-5.1s Native PHY IP core Enhanced Basic/Custom (Standard PCS) SONET/SDH OC-96
SONET/SDH STS-48/STM-16 (2.5G) via SFP/TFI-5.1 Native PHY IP core Standard Basic/Custom (Standard PCS) SONET/SDH OC-48
SONET/SDH STS-12/STM-4 (0.622G) via SFP/TFI-5.1 Native PHY IP core 7 Standard Basic/Custom (Standard PCS) SONET/SDH OC-12
SD-SDI/HD-SDI/3G/6G/12G-SDI Native PHY IP core Standard Basic/Custom (Standard PCS)

HD/3G SDI NTSC/PAL

SDI multi-rate (up to 12G) RX/TX

SDI triple-rate RX

Vx1 Native PHY IP core Standard Basic/Custom (Standard PCS) User created
DisplayPort Native PHY IP core Standard Basic/Custom (Standard PCS)

DisplayPort Duplex 4 SYMBOLS PER CLOCK

DisplayPort RX 4 SYMBOLS PER CLOCK

DisplayPort TX 4 SYMBOLS PER CLOCK

1.25G/ 2.5G

10G GPON/EPON

Native PHY IP core Enhanced Basic (Enhanced PCS) User created
2.5G/1.25G GPON/EPON Native PHY IP core Standard Basic/Custom (Standard PCS) User created
8G/4G/2G/1G Fibre Channel Native PHY IP core Standard Basic/Custom (Standard PCS) User created
SDR/DDR Infiniband x1, x4, x12 Native PHY IP core Standard Basic/Custom (Standard PCS) User created
SRIO 2.2/1.3 Native PHY IP core Standard Basic/Custom with Rate Match(Standard PCS) Serial Rapid IO 1.25 Gbps
CPRI 4.1/OBSAI RP3 v4.1 Native PHY IP core Standard CPRI (Auto)/CPRI (Manual) User created 8
SAS 3.0 Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SATA 3.0/2.0/1.0 and SAS 2.0/1.1/1.0 Native PHY IP core Standard Basic/Custom (Standard PCS)

SAS Gen2/Gen1.1/Gen1

SATA Gen3/Gen2/Gen1

HiGig/HiGig+/HiGig2/HiGig2+ Native PHY IP core Standard Basic/Custom (Standard PCS) User created
JESD204A / JESD204B Native PHY IP core Standard and Enhanced Basic/Custom (Standard PCS) Basic (Enhanced PCS) User created
Custom and other protocols Native PHY IP core

Standard and Enhanced

PCS Direct

Basis/Custom (Standard PCS)

Basic (Enhanced PCS)

Basic/Custom with Rate Match (Standard PCS)

PCS Direct

User created
1 Hard IP for PCI Express is also available as a separate IP core.
2 For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels from 8 to 4.
3

For PCIe Gen1 x1 mode, select PCIe PIPE Gen2 x1 mode. Then change the transceiver configuration rule from Gen 2 PIPE to Gen 1 PIPE.

For PCIe Gen1 x2 and x4 mode, select PCIe PIPE Gen2 x8. Then change the transceiver configuration rule from Gen2 PIPE to Gen1 PIPE and number of data channels from 8 to 2 or 4.

4

Select the 10GBASE-R preset. Then change the transceiver configuration rule from 10GBASE-R to 10GBASE-R 1588.

5 To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
6

Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP.

A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.

7 The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. If transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. If receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
8 Select CPRI 9.8 Gbps Auto/Manual Mode ( Intel® Arria® 10 only). Then change the datarate from 9830.4 Mbps to 6144 Mbps.