Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals

Figure 220. An Example of an AND Gate used as Customized LogicThe customized gates shown in the following figure are an example and not a unique solution
The capability register is not available when merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out and rx_cal_busy_out signals share the same port. So, you should build customized gating logic to separate them.
  • The tx_cal_busy_out_en signal enables the tx_cal_busy output.
  • The rx_cal_busy_out_en signal enables the rx_cal_busy output.
  • At power up, tx_cal_busy_out_en and rx_cal_busy_out_en should be set to “1”.
  • At normal operation:
    • When the RX is calibrating, setting tx_cal_busy_out_en to “0” and rx_cal_busy_out_en to “1” disables tx_cal_busy, so the TX does not reset while RX is calibrating.
    • When the TX is calibrating, setting rx_cal_busy_out_en to “0” and tx_cal_busy_out_en to “1” disables rx_cal_busy, so the RX does not reset while TX is calibrating.