Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

5.1.3. Transmitter Buffer

The transmitter buffer includes the following circuitry:

  • High Speed Differential I/O
  • Programmable differential output voltage (VOD)
    • Main tap
  • Programmable four-tap pre-emphasis circuitry
    • Two pre-cursor taps
    • Two post-cursor taps
  • Power distribution network (PDN) induced inter-symbol interference (ISI) compensation
  • Internal termination circuitry
  • Receiver detect capability to support the PCI Express configuration
Figure 169. Transmitter Buffer