Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents PRBS Checker

You can use Cyclone 10 GX pseudo-random bit stream (PRBS) checker to easily characterize high-speed links without developing or fully implementing any upper layer of a protocol stack. The PRBS checker in Cyclone 10 GX devices is a shared hardened block between the Standard and Enhanced datapaths. Hence, there is only one set of control signals and registers for this feature.

You can use the PRBS checker block to verify the pattern generated by the PRBS generator. The PRBS checker can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS checker patterns can only be used when the PCS-PMA interface width is configured to 10 bits or 64 bits.

The pseudo-random bit stream (PRBS) block verifies the pattern generated by the PRBS generator. The verifier supports the 64-bit PCS-PMA interface. PRBS7 supports 64-bit width only. PRBS9 supports 10-bit PMA data width to allow testing at a lower data rate.

Table 181.  Supported PRBS Patterns
PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA width
PRBS7: x7 + x6 + 1  


PRBS9: x9 + x5 + 1



PRBS15: x15 + x14 + 1



PRBS23: x23 + x18 + 1



PRBS31: x31 + x28 + 1



Figure 188. PRBS9 Verify Serial Implementation

The PRBS checker has the following control and status signals available to the FPGA fabric:

  • rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr.
  • rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
  • rx_prbs_err_clr—Used to reset the rx_prbs_err signal.

Enable the PRBS checker control and status ports through the Native PHY IP Parameter Editor in the Quartus Prime software.