Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

4.4.4. Transceiver PHY Reset Controller Resource Utilization

This section describes the estimated device resource utilization for two configurations of the transceiver PHY reset controller. The exact resource count varies by Quartus Prime version number, as well as by optimization options.
Table 174.   Reset Controller Resource Utilization


Combination ALUTs

Logic Registers

Single transceiver channel

approximately 50

approximately 50

Four transceiver channels, shared TX reset, separate RX resets

approximately 100

approximately 150