Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents How to Implement GbE, GbE with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.

  1. Instantiate the Intel® Cyclone® 10 GX Transceiver Native PHY IP from the IP Catalog.
  2. Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
  3. Use the parameter values in the tables in Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. Use the GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE 1588. You can then modify the setting to meet your specific requirements.
  4. Click Generate to generate the Native PHY IP core top-level RTL file.
    Figure 41. Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2Generating the IP core creates signals and ports based on your parameter settings.

  5. Instantiate and configure your PLL.
  6. Instantiate a transceiver reset controller.
    You can use your own reset controller or use the Native PHY Reset Controller IP core.
  7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in the figure below to connect the ports.
    Figure 42.  Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design

  8. Simulate your design to verify its functionality.