Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

7.2. Calibration Registers

The Cyclone® 10 GX transceiver PMA and PLLs include the following types of registers for calibration:

  • Avalon-MM interface arbitration registers
  • Calibration enable registers
  • Capability registers
  • Rate switch flag registers

The Avalon-MM interface arbitration registers enable you to request internal configuration bus access.

The PMA and PLL calibration enable registers for user recalibration are mapped to offset address 0x100. All calibration enable registers are self-cleared after the calibration process is completed.

The tx_cal_busy, rx_cal_busy, ATX PLL pll_cal_busy, and fPLL pll_cal_busy signals are available from the capability registers.

The rate switch flag registers are only used for CDR rate change.