Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

4.5. Using a User-Coded Reset Controller

You can design your own user-coded reset controller instead of using Transceiver PHY Reset Controller. Your user-coded reset controller must provide the following functionality for the recommended reset sequence:
  • A clock signal input for your reset logic
  • Holds the transceiver channels in reset by asserting the appropriate reset control signals
  • Checks the PLL status (for example, checks the status of pll_locked and pll_cal_busy)
Note: You must ensure a stable reference clock is present at the PLL transmitter before releasing pll_powerdown.