Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

7.5.1. ATX PLL Recalibration

When you use the ATX PLL in your application, and it requires a line rate or clock frequency change, you must recalibrate the ATX PLL after you have made the changes.

Follow these steps to recalibrate the ATX PLL:

  1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
  2. Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
  3. To calibrate the ATX PLL, perform a Read-Modify-Write of 0x1 to bit[0] of address 0x100 of the ATX PLL.
  4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
  5. Periodically check the *cal_busy output signals or read the capability registers 0x280[1] to check *cal_busy status until calibration is complete.

You should avoid recalibrating the ATX PLL if another TX channel is in transmitting mode (clocked by another ATX PLL in the device). You need to do this to prevent a potential BER on neighboring RX channel placed next to a TX channel clocked by the ATX PLL. You can recalibrate the ATX PLL only if:

  1. The other TX channel that is in transmitting mode is clocked by fPLL or
  2. The other TX channel (clocked by another ATX PLL) must be place under reset condition.