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There are two fPLLs in each transceiver bank with six channels (one located at the top and the other at the bottom of the bank). Transceiver banks with three channels have only one fPLL.
When in core mode, for the fPLL to generate output clocks with a fixed frequency and phase relation to an input reference clock, the Enable phase alignment option must be selected. In the fractional frequency mode, the fPLL supports data rates from 1 Gbps to 12.5 Gbps.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
- Dedicated reference clock pin
- Reference clock network
- Receiver input pin
- Output of another fPLL with PLL cascading
- Global clock or the core clock network
The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for best jitter performance. For protocol jitter compliance at datarate > 10 Gbps, Intel® recommends using the dedicated reference clock pin in the same triplet with the fPLL as the input reference clock source. The input reference clock must be stable and free-running at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.
Reference Clock MultiplexerThe refclk mux selects the reference clock to the PLL from the various available reference clock sources.
N CounterThe N counter divides the reference clock (refclk) mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency within the phase frequency detector's (PFD) operating range. The N counter supports division factors from 1 to 32.
Phase Frequency DetectorThe reference clock (refclk) signal at the output of the N counter block and the feedback clock (fbclk) signal at the output of the M counter block are supplied as an inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk and fbclk inputs. The PFD aligns the fbclk to the refclk. The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency.
Voltage Controlled Oscillator
The fPLL has a ring oscillator based VCO. The VCO transforms the input control voltage into an adjustable frequency clock.
VCO freq = 2 * M * Input reference clock/N. (N and M are the N counter and M counter division factors.)
L CounterThe L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL, the output of the L counter drives the clock generation block (CGB) and the TX PMA via the X1 clock lines.
The M counter divides the VCO's clock output. The M counter can select any VCO phase. The outputs of the M counter and N counter have same frequency. M counter range is 8 to 127 in integer mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis.
In fractional mode, the M value is as follows:
M (integer) + K/2^32, where K is the fractional multiply factor (K) in the fPLL IP Parameter Editor. The legal values of K are greater than 1% and less than 99% of the full range of 2^32 and can only be manually entered in the fPLL IP Parameter Editor in the Quartus Prime software.
The output frequencies can be exact when the fPLL is configured in fractional mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in the K-precision mode (K < 0.1 or K > 0.9).
The fPLL C counter division factors range from 1 to 512.
Dynamic Phase Shift
The dynamic phase shift block allows you to adjust the phase of the C counters in user mode. In fractional mode, dynamic phase shift is only available for the C counters.
The C counters can be configured to select any VCO phase and a delay of up to 128 clock cycles. The selected VCO phase can be changed dynamically.
Instantiating the fPLL IP Core
fPLL IP Core
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