Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Receiver Detection

The PIPE interface block in Cyclone® 10 GX transceivers provides an input signal pipe_tx_detectrx_loopback[0:0] for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state of the LTSSM. When the pipe_tx_detectrx_loopback[0:0] signal is asserted in the P1 power state, the PIPE interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. The time constant of the step voltage on the trace increases if an active receiver that complies with the PCIe input impedance requirements is present at the far end. The receiver detect circuitry monitors this time constant to determine if a receiver is present.

Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be used. Also, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification 2.0.

The PIPE core provides a 1-bit PHY status signal pipe_phy_status[0:0] and a 3-bit receiver status signal pipe_rx_status[2:0] to indicate whether a receiver is detected, as per the PIPE 2.0 specifications.