Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Implementing x6/xN Bonding Mode

Figure 142. PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode

Steps to implement a x6/xN bonded configuration

  1. You can instantiate either the ATX PLL or the fPLL for x6/xN bonded configuration.
    • The CMU PLL cannot drive the Master CGB, only the ATX PLL or fPLL can be used for bonded configurations.
  2. Configure the PLL IP core using the IP Parameter Editor. Enable Include Master Clock Generation Block and Enable bonding clock output ports.
  3. Configure the Native PHY IP core using the IP Parameter Editor .
    • Set the Native PHY IP core TX Channel bonding mode to either PMA bonding or PMA/PCS bonding .
    • Set the number of channels required by your design. In this example, the number of channels is set to 10.
  4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.
    • In this case, the PLL IP core has tx_bonding_clocks output bus with width [5:0].
    • The Native PHY IP core has tx_bonding_clocks input bus with width [5:0] multiplied by the number of transceiver channels (10 in this case). For 10 channels, the bus width is [59:0].
      Note: While connecting tx_bonding_clocks, leave pll_ref_clk open to avoid any Quartus Prime software fitter errors.
    • Connect the PLL IP core to the PHY IP core by duplicating the output of the PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for the input port connection is .tx_bonding_clocks ({10{tx_bonding_clocks_output}}) .
Note: Although the above diagram looks similar to the 10-channel non-bonded configuration example, the clock input ports on the transceiver channels bypass the local CGB in x6/xN bonding configuration. This internal connection is taken care of when the Native PHY channel bonding mode is set to Bonded.
Figure 143. x6/xN Bonding Mode —Internal Channel Connections

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