Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Resetting the Transceiver Channel During Device Operation

The numbers in this list correspond to the numbers in the following figure.

  1. Assert tx_analogreset, pll_powerdown, tx_digitalreset, rx_analogreset, and rx_digitalreset. Ensure that pll_cal_busy, tx_cal_busy, and rx_cal_busy are low.
  2. Deassert pll_powerdown and tx_analogreset at the same time, after a minimum duration of 70 μs.
  3. The pll_locked signal goes high after the TX PLL acquires lock. Wait for a minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked signal.
  4. Deassert tx_digitalreset after pll_locked goes high. The tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset (minimum of 70 μs) duration after tx_analogreset is deasserted.
  5. Deassert rx_analogreset after deasserting tx_analogreset.
  6. Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before deasserting rx_digitalreset.
Figure 152. Resetting the Transceiver Channel During Device Operation