Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents PCIe Reverse Parallel Loopback

PCIe reverse parallel loopback is only available in a PCIe functional configuration for Gen1 and Gen2 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the rx_parallel_data port. This loopback mode is based on PCIe specification 2.0. Cyclone® 10 GX devices provide an input signal pipe_tx_detectrx_loopback[0:0] to enable this loopback mode.

Note: This is the only loopback option supported in PIPE configurations.
Figure 62. PCIe Reverse Parallel Loopback Mode Datapath