Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your Basic protocol IP.

  1. Open the IP Catalog and select the Native PHY IP.
  2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match (Standard PCS) from the Transceiver configuration rules list located under Datapath Options depending on which configuration you want to use.
  3. Use the parameter values in the tables in Transceiver Native PHY IP Parameter Settings for the Basic Protocol as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. You can then modify the setting to meet your specific requirements.
  4. Click Finish to generate the Native PHY IP (this is your RTL file).
    Figure 112. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match Configurations

  5. Instantiate and configure your PLL.
  6. Create a transceiver reset controller.
  7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in Transceiver Native PHY Ports for the Protocol to connect the ports.
    Figure 113. Connection Guidelines for a Basic/Custom Design
  8. Simulate your design to verify its functionality.