Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

7. Calibration

Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Cyclone® 10 GX transceiver uses hardened Precision Signal Integrity Calibration Engine (PreSICE) to perform calibration routines.

Power-up Calibration and User Recalibration are the main types of calibration.

  • Power-up calibration occurs automatically at device power-up. It runs during device configuration.
  • If you perform dynamic reconfiguration, then you must perform User Recalibration. In this case, you are responsible for enabling the required calibration sequence.
  • If you need to reconfigure the ATX PLL, use TX PLL switching mode or use local clock divider to achieve the new data rate and avoid recalibrating the ATX PLL.
  • If you are recalibrating your fPLL, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" section in PLLs and Clock Networks chapter.

Cyclone® 10 GX devices use CLKUSR for clocking the transceiver calibration. To successfully complete the calibration process, the CLKUSR clock must be within specification, stable and free running at the start of FPGA configuration. Also, all reference clocks driving transceiver PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. For more information about CLKUSR pin requirements, refer to the Cyclone® 10 GX GX, GT, and SX Device Family Pin Connection Guidelines