Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model

The numbers in this list correspond to the numbers in the following figure.

  1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while pll_cal_busy and tx_cal_busy are low.
  2. Wait for tx_analogreset_ack to go high, to ensure successful assertion of tx_analogreset. tx_analogreset_ack goes high when TRS has successfully completed the reset request for assertion.
    1. Perform dynamic reconfiguration.
    2. Deassert pll_powerdown after tpll_powerdown.
    3. Deassert tx_analogreset. This step can be done at the same time or after you deassert pll_powerdown.
  3. Wait for tx_analogreset_ack to go low, to ensure successful deassertion of tx_analogreset. tx_analogreset_ack goes low when TRS has successfully completed the reset request for deassertion.
  4. The pll_locked signal goes high after the TX PLL acquires lock. Wait for tx_analogreset_ack to go low before monitoring the pll_locked signal.
  5. Deassert tx_digitalreset a minimum ttx_digitalreset time after pll_locked goes high.
Figure 159. Dynamic Reconfiguration of Transmitter Channel During Device Operation