Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

7.4.2. User Recalibration Sequence

Figure 223. User Recalibration Sequence for ATX PLL, fPLL and Native PHY IP (RX PMA / TX PMA)

User recalibration requires access to the internal configuration bus and calibration registers through the Avalon® -MM reconfiguration interface. Follow the recalibration example steps detailed in Calibration Example to perform a user recalibration process for each ATX PLL IP, fPLL IP and Native PHY IP (RX PMA / TX PMA).