Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Word Aligner Bit Slip Mode

In bit slip mode, the word aligner operation is controlled by rx_bitslip, which has to be held for two parallel clock cycles. At every rising edge of rx_bitslip, the bit slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Pattern detection is not used in bit slipping mode; therefore, rx_syncstatus is not valid in this mode.