Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents Transmitter and Receiver Latency

The latency variation from the link synchronization function (in the word aligner block) is deterministic with the rx_bitslipboundaryselectout port. Additionally, you can use the tx_bitslipboundaryselect port to fix the round trip transceiver latency for port implementation in the remote radio head to compensate for latency variation in the word aligner block. The tx_bitslipboundaryselect port is available to control the number of bits to be slipped in the transmitter serial data stream. You can optionally use the tx_bitslipboundaryselect port to round the round-trip latency to a whole number of cycles.

When using the byte deserializer, additional logic is required in the FPGA fabric to determine if the comma byte is received in the lower or upper byte of the word. The delay is dependent on the word in which the comma byte appears.

Note: Latency numbers are pending device characterization.