Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Document Table of Contents

3.7. Receiver Data Path Interface Clocking

The CDR block present in the PMA of each channel recovers the serial clock from the incoming data. The CDR block also divides the recovered serial clock to generate the recovered parallel clock. Both the recovered serial and the recovered parallel clocks are used by the deserializer. The receiver PCS can use the following clocks based on the configuration of the receiver channel:

  • Recovered parallel clock from the CDR in the PMA
  • Parallel clock from the clock divider used by the transmitter PCS (if enabled) for that channel

For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the byte deserializer and the write side of the RX phase compensation FIFO.

Figure 131. Receiver Standard PCS and PMA Clocking

All configurations that use the standard PCS channel must have a 0 ppm phase difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.

Figure 132. Receiver Enhanced PCS and PMA Clocking

The receiver PCS forwards the following clocks to the FPGA fabric:

  • rx_clkout — for each receiver channel when the rate matcher is not used.
  • tx_clkout — for each receiver channel when the rate matcher is used.

You can clock the receiver datapath interface using one of the following methods:

  • Quartus Prime selected receiver datapath interface clock
  • User-selected receiver datapath interface clock