- 188.8.131.52. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
- 184.108.40.206. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
- 220.127.116.11. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
Interlaken is a scalable, channelized chip-to-chip interconnect protocol.
The key advantages of Interlaken are scalability and low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking. Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst semantics include integrity checking and per logical channel flow control.
The Interlaken interface is supported with 1 to 12 lanes running at data rates up to 12.5 Gbps per lane on Cyclone® 10 GX devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.
Cyclone® 10 GX devices provide three preset variations for Interlaken in the Cyclone® 10 GX Transceiver Native PHY IP Parameter Editor:
- Interlaken 10x12.5 Gbps
- Interlaken 1x6.25 Gbps
- Interlaken 6x10.3 Gbps
Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of 32, 40, or 64 bits.
Metaframe Format and Framing Layer Control Word
Interlaken Configuration Clocking and Bonding
How to Implement Interlaken in Cyclone 10 GX Transceivers
Native PHY IP Parameter Settings for Interlaken
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